module muxregext (X, Y, Z, SEL, OUT);

input [7:0] X, Y, Z;
input [1:0] SEL;
output [7:0] OUT;

wire [7:0] X, Y, Z;
wire [1:0] SEL;
reg [7:0] OUT;

always @ (X or Y or Z or SEL)
begin
	case (SEL)
	2'b00: OUT = X;
	2'b01: OUT = Y;
	2'b10: OUT = Z;
	2'b11: OUT = 8'bz;
	endcase
end

endmodule